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ISL6208A
Data Sheet February 15, 2006 FN9272.0
High Voltage Synchronous Rectified Buck MOSFET Driver
The ISL6208A is a high frequency, dual MOSFET driver, optimized to drive two N-Channel power MOSFETs in a synchronous-rectified buck converter topology. It is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. This driver, combined with an Intersil multiphase Buck PWM controller, forms a complete single-stage core-voltage regulator solution for advanced mobile microprocessors. The ISL6208A features 4A typical sinking current for the lower gate driver. This current is capable of holding the lower MOSFET gate off during the rising edge of the Phase node. This prevents shoot-through power loss caused by the high dv/dt of phase voltages. The operating voltage matches the 30V breakdown voltage of the MOSFETs commonly used in mobile computer power supplies. The ISL6208A also features a three-state PWM input that, working together with Intersil's multiphase PWM controllers, will prevent negative voltage output during CPU shutdown. This feature eliminates a protective Schottky diode usually seen in a microprocessor power systems. MOSFET gates can be efficiently switched up to 2MHz using the ISL6208A. Each driver is capable of driving a 3000pF load with propagation delays of 15ns and transition times under 10ns. Bootstrapping is implemented with an internal Schottky diode. This reduces system cost and complexity, while allowing the use of higher performance MOSFETs. Adaptive shoot-through protection is integrated to prevent both MOSFETs from conducting simultaneously. A diode emulation feature is integrated in the ISL6208A to enhance converter efficiency at light load conditions. This feature also allows for monotonic start-up into pre-biased outputs. When diode emulation is enabled, the driver will allow discontinuous conduction mode by detecting when the inductor current reaches zero and subsequently turning off the low side MOSFET gate. Programmable dead-time control with gate threshold monitoring is also integrated to prevent both MOSFETs from conducting simultaneously.
Features
* Dual MOSFET Drives for Synchronous Rectified Bridge * Adaptive Shoot-Through Protection - Active Gate Threshold Monitoring - Programmable Dead-Time * 0.5 On-Resistance and 4A Sink Current Capability * Supports High Switching Frequency up to 2MHz - Fast Output Rise and Fall Time - Low Propagation Delay * * * * * * Three-State PWM Input for Power Stage Shutdown Internal Bootstrap Schottky Diode Low Bias Supply Current (5V, 100A) Diode Emulation for Efficiency and Pre-Biased Startup VCC POR (Power-On-Reset) Feature Integrated Pin-to-pin Compatible with ISL6207, ISL6208, ISL6209
* QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Supplies for Intel(R) and AMD(R) Mobile Microprocessors * High Frequency, Low Profile DC/DC Converters * High Current Low Output Voltage DC/DC Converters * High Input Voltage DC/DC Converters
Ordering Information
PART NUMBER ISL6208ACBZ (Note) PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. # M8.15
ISL6208ACBZ -10 to 100 8 Ld SOIC (Pb-Free)
ISL6208ACBZ-T ISL6208ACBZ 8 Ld SOIC Tape and Reel (Note) (Pb-Free) ISL6208ACRZ (Note) 08AZ -10 to 100 8 Ld 3x3 QFN L8.3x3 (Pb-Free) 8 Ld 3x3 QFN Tape and Reel (Pb-Free)
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Technical Brief TB389 "PCB Land Pattern Design and Surface Mount Guidelines for MLFP Packages" * Technical Brief TB447 "Guidelines for Preventing Boot-toPhase Stress on Half-Bridge MOSFET Driver ICs" 1
ISL6208ACRZ-T 08AZ (Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6208A Pinouts
ISL6208ACB (8 LD SOIC) TOP VIEW ISL6208ACR (8 LD 3x3 QFN) TOP VIEW
PHASE 7 6 6 FCCM 5 VCC 3 GND 4 LGATE tFU UGATE 8 BOOT 1 PWM 2 SHOOTTHROUGH PROTECTION PWM 10K CONTROL LOGIC VCC LGATE GND THERMAL PAD (FOR QFN PACKAGE ONLY)
UGATE BOOT PWM GND
1 2 3 4
8 7 6 5
PHASE FCCM VCC LGATE
Block Diagram
VCC FCCM
BOOT UGATE PHASE
FIGURE 1. BLOCK DIAGRAM
Timing Diagram
2.5V PWM tPDHU tPDLU tRU tRU tPTS 1V UGATE LGATE 1V tFL tPDLL tPDHL tFL tRL tTSSHD tTSSHD
tFU
tPTS
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ISL6208A
Absolute Maximum Ratings
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Input Voltage (VFCCM, VPWM). . . . . . . . . . . . . -0.3V to VCC + 0.3V BOOT Voltage (VBOOT-GND). . . . . . . . . . . . . . . . . . . . . -0.3V to 33V BOOT To PHASE Voltage (VBOOT-PHASE) . . . . . . -0.3V to 7V (DC) -0.3V to 9V (<10ns) PHASE Voltage (Note 1) . . . . . . . . . . . . . . . . . . . GND - 0.3V to 30V GND -8V (<20ns Pulse Width, 10J) UGATE Voltage . . . . . . . . . . . . . . . . VPHASE - 0.3V (DC) to VBOOT VPHASE - 5V (<20ns Pulse Width, 10J) to VBOOT LGATE Voltage . . . . . . . . . . . . . . . GND - 0.3V (DC) to VCC + 0.3V GND - 2.5V (<20ns Pulse Width, 5J) to VCC + 0.3V Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40C to 125C
Thermal Information
Thermal Resistance (Typical Notes 2, 3, 4) JA (C/W) JC (C/W) SOIC Package (Note 2) . . . . . . . . . . . . 110 n/a QFN Package (Notes 3, 4). . . . . . . . . . 80 15 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to 150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300C (SOIC - Lead Tips Only)
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-10C to 100C Maximum Operating Junction Temperature. . . . . . . . . . . . . . 125C Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. The Phase Voltage is capable of withstanding -7V DC when the BOOT pin is at GND. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Bias Supply Current POR
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC
PWM pin floating, VFCCM = 5V Vcc Rising Vcc Falling
2.40 -
100 3.30 2.90 400
3.90 -
A V V mV
POR Hysteresis BOOTSTRAP DIODE Forward Voltage PWM INPUT Input Current IPWM VPWM = 5V, VFCCM = 5V VPWM = 0V, VFCCM = 5V PWM Three-State Rising Threshold PWM Three-State Falling Threshold Three-State Shutdown Holdoff Time UG/LG Three-state Propagation Delay FCCM INPUT FCCM Threshold FCCM Transient Delay SWITCHING TIME UGATE Rise Time (Note 5) LGATE Rise Time (Note 5) UGATE Fall Time (Note 5) tRU tRL tFU VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load VVCC = 5V, 3nF Load RSET = 0 tTSSHD tPTS VVCC = 5V VVCC = 5V VVCC = 5V, temperature = 25C VF VVCC = 5V, forward bias current = 2mA
0.45
0.60
0.65
V
0.70 3.5 -
250 -250 1.00 3.8 70 20
1.30 4.1 -
A A V V ns ns
-
2.5 70
-
V ns
-
8.0 8.0 8.0
-
ns ns ns
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FN9272.0 February 15, 2006
ISL6208A
Electrical Specifications
PARAMETER LGATE Fall Time (Note 5) UGATE Turn-Off Propagation Delay LGATE Turn-Off Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay UGATE Turn-On Propagation Delay LGATE Turn-On Propagation Delay Minimum LG On TIME in DCM (Note 5) OUTPUT Upper Drive Source Resistance (Note 5) Upper Driver Source Current (Note 5) Upper Drive Sink Resistance (Note 5) Upper Driver Sink Current (Note 5) Lower Drive Source Resistance (Note 5) Lower Driver Source Current (Note 5) Lower Drive Sink Resistance (Note 5) Lower Driver Sink Current (Note 5) NOTE: 5. Guaranteed by Characterization. Not 100% Tested in Production. RU IU RU IU RL IL RL IL 500mA Source Current VUGATE-PHASE = 2.5V 500mA Sink Current VUGATE-PHASE = 2.5V 500mA Source Current VLGATE = 2.5V 500mA Sink Current VLGATE = 2.5V 1 2.00 1 2.00 1 2.00 0.4 4.00 2.5 2.5 2.5 1.0 A A A A Recommended Operating Conditions, Unless Otherwise Noted (Continued) SYMBOL tFL tPDLU tPDLL tPDHU tPDHL tPDHU tPDHL tLGMIN TEST CONDITIONS VVCC = 5V, 3nF Load VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded VVCC = 5V, Outputs Unloaded; RSET = 0 VVCC = 5V, Outputs Unloaded; RSET = 0 VVCC = 5V, Outputs Unloaded; RSET = 80k VVCC = 5V, Outputs Unloaded; RSET = 80k MIN TYP 4.0 20 27 26 26 41 33 400 MAX UNITS ns ns ns ns ns ns ns ns
Typical Application with 2-Phase Converter
+5V +5V +5V VCC FB VCC VSEN PGOOD PWM1 PWM2 FCCM MAIN CONTROL VID ISEN1 +5V ISEN2 FCCM VCC BOOT UGATE DRIVE ISL6208A PHASE VBAT COMP FCCM PWM BOOT UGATE PHASE DRIVE ISL6208A THERMAL PAD LGATE VBAT +VCORE
FS
DACOUT GND
PWM
THERMAL LGATE PAD
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ISL6208A Functional Pin Description
UGATE (Pin 1 for SOIC-8, Pin 8 for QFN)
The UGATE pin is the upper gate drive output. Connect to the gate of high-side power N-Channel MOSFET.
PHASE (Pin 8 for SOIC-8, Pin 7 for QFN)
Connect the PHASE pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver.
BOOT (Pin 2 for SOIC-8, Pin 1 for QFN)
BOOT is the floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Bootstrap Diode and Capacitor section under DESCRIPTION for guidance in choosing the appropriate capacitor value.
Description
Theory of Operation
Designed for speed, the ISL6208A dual MOSFET driver controls both high-side and low-side N-Channel FETs from one externally provided PWM signal. A rising edge on PWM initiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [tPDLL], the lower gate begins to fall. Typical fall times [tFL] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage. When LGATE has fallen below 1V, UGATE is allowed to turn ON. This prevents both the lower and upper MOSFETs from conducting simultaneously, or shootthrough. A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [tPDLU] is encountered before the upper gate begins to fall [tFU]. The upper MOSFET gate-to-source voltage is monitored, and the lower gate is allowed to rise after the upper MOSFET gate-to-source voltage drops below 1V. The lower gate then rises [tRL], turning on the lower MOSFET. This driver is optimized for converters with large step down compared to the upper MOSFET because the lower MOSFET conducts for a much longer time in a switching period. The lower gate driver is therefore sized much larger to meet this application requirement. The 0.5 on-resistance and 4A sink current capability enable the lower gate driver to absorb the current injected to the lower gate through the drain-to-gate capacitor of the lower MOSFET and prevent a shoot through caused by the high dv/dt of the phase node.
PWM (Pin 3 for SOIC-8, Pin 2 for QFN)
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation (see the three-state PWM Input section under DESCRIPTION for further details). Connect this pin to the PWM output of the controller.
GND (Pin 4 for SOIC-8, Pin 3 for QFN)
GND is the ground pin for the IC.
LGATE (Pin 5 for SOIC-8, Pin 4 for QFN)
LGATE is the lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
VCC (Pin 6 for SOIC-8, Pin 5 for QFN)
Connect the VCC pin to a +5V bias supply. Place a high quality bypass capacitor from this pin to GND.
FCCM (Pin 7 for SOIC-8, Pin 6 for QFN)
The FCCM pin enables or disables Diode Emulation. When FCCM is LOW, diode emulation is allowed. Otherwise, continuous conduction mode is forced. See the Diode Emulation section under DESCRIPTION for more detail. This pin can also be used to program additional switching dead-time by placing a resistor in series with the input. See the Programmable Dead-Time section for more detail.
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FN9272.0 February 15, 2006
ISL6208A Typical Performance Waveforms
FIGURE 2. LOAD TRANSIENT (0 - 30A, 3-PHASE)
FIGURE 3. LOAD TRANSIENT (30 - 0A, 3-PHASE)
FIGURE 4. DCM TO CCM TRANSITION AT NO LOAD
FIGURE 5. CCM TO DCM TRANSITION AT NO LOAD
FIGURE 6. PRE-BIASED STARTUP IN CCM MODE
FIGURE 7. PRE-BIASED STARTUP IN DCM MODE
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ISL6208A
Diode Emulation
Diode emulation allows for higher converter efficiency under light-load situations. With diode emulation active, the ISL6208A will detect the zero current crossing of the output inductor and turn off LGATE. This ensures that discontinuous conduction mode (DCM) is achieved. Diode emulation is asynchronous to the PWM signal. Therefore, the ISL6208A will respond to the FCCM input immediately after it changes state. Refer to the waveforms on page 6.
NOTE: Intersil does not recommend DCM mode use with rDS(ON) current sensing topologies. The turn-OFF of the low side MOSFET can cause gross current measurement inaccuracies.
FCCM = VCC or GND GATE B
GATE A
Adaptive Shoot-Through Protection 1V
Three-State PWM Input
A unique feature of the ISL6208A and other Intersil drivers is the addition of a shutdown window to the PWM input. If the PWM signal enters and remains within the shutdown window for a set holdoff time, the output drivers are disabled and both MOSFET gates are pulled and held low. The shutdown state is removed when the PWM signal moves outside the shutdown window. Otherwise, the PWM rising and falling thresholds outlined in the ELECTRICAL SPECIFICATIONS determine when the lower and upper gates are enabled.
FCCM = RESISTOR to VCC or GND GATE A GATE B
Adaptive Protection with Delay
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection to prevent upper and lower MOSFETs from conducting simultaneously and shorting the input supply. This is accomplished by ensuring the falling gate has turned off one MOSFET before the other is allowed to turn on. During turn-off of the lower MOSFET, the LGATE voltage is monitored until it reaches a 1V threshold, at which time the UGATE is released to rise. Adaptive shoot-through circuitry monitors the upper MOSFET gate-to-source voltage during UGATE turn-off. Once the upper MOSFET gate-to-source voltage has dropped below a threshold of 1V, the LGATE is allowed to rise. In addition to gate threshold monitoring, a programmable delay between MOSFET switching can be accomplished by placing a resistor in series with the FCCM input. This delay allows for maximum design flexibility over MOSFET selection. The delay can be programmed from 5ns to 50ns above the adaptive shoot-through protection and is obtained from the absolute value of the current flowing into the FCCM pin. If no resistor is used, the minimum 5ns delay is used. Gate threshold monitoring is not affected by the addition or removal of the additional dead-time. Refer to Figure 8 and Figure 9 for more detail.
DEAD-TIME (ns) 1V
tdelay = 5n - 50ns
FIGURE 8. PROGRAMMABLE DEAD-TIME
50 45 40 35 30 25 20 15 10 5 0 0 167 333 500 RDELAY (k) 667 833 1000 tDELAY
FIGURE 9. ISL6208A PROGRAMMABLE DEAD-TIME vs DELAY RESISTOR
The equation governing the dead-time seen in Figure 9 is expressed as:
T DELAY ( ns ) = [ 0.045 x R DELAY ( k ) ] + 5ns
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FN9272.0 February 15, 2006
ISL6208A
The equation can be rewritten to solve for RDELAY as follows:
( T DELAY ( ns ) - 5ns ) R DELAY ( k ) = -----------------------------------------------------0.045
frequency for the selected MOSFETs. The power dissipated by the driver is approximated as:
P = f sw ( 1.5V U Q + V L Q ) + I VCC V U L CC (EQ. 2)
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode. Simply adding an external capacitor across the BOOT and PHASE pins completes the bootstrap circuit. The bootstrap capacitor must have a maximum voltage rating above the maximum battery voltage plus 5V. The bootstrap capacitor can be chosen from the following equation:
Q GATE C BOOT ----------------------V BOOT (EQ. 1)
where fsw is the switching frequency of the PWM signal. VU and VL represent the upper and lower gate rail voltage. QU and QL is the upper and lower gate charge determined by MOSFET selection and any external capacitance added to the gate pins. The lVCC VCC product is the quiescent power of the driver and is typically negligible.
1000 900 800 700 POWER (mW) 600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (kHz) QU =20nC QL=50nC QU =100nC QL =200nC QU =50nC QL =100nC QU =50nC QL=50nC
where QGATE is the amount of gate charge required to fully charge the gate of the upper MOSFET. The VBOOT term is defined as the allowable droop in the rail of the upper drive. As an example, suppose an upper MOSFET has a gate charge, QGATE , of 25nC at 5V and also assume the droop in the drive voltage over a PWM cycle is 200mV. One will find that a bootstrap capacitance of at least 0.125F is required. The next larger standard value capacitance is 0.15F. A good quality ceramic capacitor is recommended.
2.0 1.8 1.6 CBOOT_CAP (F) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 20nC 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VBOOT_CAP (V) 0.8 0.9 1.0 QGATE = 100nC
nC 50
FIGURE 11. POWER DISSIPATION vs FREQUENCY
0.0 0.0
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE VOLTAGE
Power Dissipation
Package power dissipation is mainly a function of the switching frequency and total gate charge of the selected MOSFETs. Calculating the power dissipation in the driver for a desired application is critical to ensuring safe operation. Exceeding the maximum allowable power dissipation level will push the IC beyond the maximum recommended operating junction temperature of 125C. The maximum allowable IC power dissipation for the SO-8 package is approximately 800mW. When designing the driver into an application, it is recommended that the following calculation be performed to ensure safe operation at the desired
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FN9272.0 February 15, 2006
ISL6208A Quad Flat No-Lead Plastic Package (QFN)
L8.3x3
8 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VEEC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 0.60 8 2 2 0.60 12 0.25 0.25 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 3.00 BSC 2.75 BSC 1.10 3.00 BSC 2.75 BSC 1.10 0.65 BSC 0.75 0.15 1.25 1.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 10/02 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN9272.0 February 15, 2006
ISL6208A Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0 8 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN9272.0 February 15, 2006

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